Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput, thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc) has been built up around this technology.
In this process, a mask, or “reticle,” includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics/lenses that project light coming through the reticle and image the circuit pattern, typically with a 4× to 5× reduction factor, on a photoresist film formed on a silicon wafer. The term chrome refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material may also vary such as in the case of an attenuating phase shift mask.
FIG. 1 is an example of a conventional optical projection lithography apparatus. As illustrated in FIG. 1, the optical projection lithography apparatus includes a light source 20, a photomask 22, and reduction optics 24. A wafer 26, having a layer of photo-resist 28 thereon, is placed within the optical projection lithography apparatus, and the light-source 20 generates a beam of light 21 that is incident upon the photomask 22. The reduction optics 24 projects the light beam to cause a pattern 30 that exposes the photo-resist layer 28, creating the pattern 30 of reacted material in the resist layer 28. In this manner, a pattern 32, provided on the mask 22, is transferred to the photo-resist layer 28 on the wafer 26.
The photo-resist pattern 30 is then transferred to the underlying wafer 26 through standard etching processes using standard semiconductor fabrication techniques. Both positive and negative tone resists can be used to produce either positive or negative images of the mask pattern on the wafer.
An example of a phase shift mask is illustrated in FIGS. 2 and 3. As illustrated in FIGS. 2 and 3, a dense-feature mask example 220 is a phase-shift mask comprising a grating pattern of periodic features. It is noted that a dense grating pattern is only one example of a dense-feature mask. FIGS. 2 and 3 are top and side views, respectively, of the phase-shift mask 220. The phase-shift mask 220 may be formed of, for example, fused SiO2. Periodic trenches 23 are formed in the mask 220 to provide an interference pattern upon illumination that results in the desired photoresist pattern 30 on the wafer 26.
In the chromeless phase shift mask 220, periodic features or trenches 23 are typically etched into the transparent mask material, which is typically quartz. The depth of these etched features 23 results in a relative phase difference in the illumination that is transmitted on either side of a phase boundary 36. When the relative phase difference is 180 degrees, an interference null corresponding to the phase edge 36 is produced at the image plane, which is typically the wafer or substrate 26. It is noted that chromeless phase shift masks illustrated here are only one type of phase shift mask. There are many other types of phase shift masks.
As the semiconductor industry continues to evolve and grow, feature sizes of the pattern are driven to an ever-smaller resolution. The driving force is the desire of these industries to remain on the “Moore's Law” growth curve. The “Moore's Law” growth curve calls for an exponential increase of circuit density versus production year that is typically accomplished by decreasing feature sizes. However, the resolution of an optical stepper is limited by the wavelength of the light source, and is further limited by the numerical aperture (“NA”) of the lens.
The basic lithographic imaging relationships are:Resolution=k1λ/NA; and  1)Depth of Focus=k2λ/(NA)2;  2)where λ is the illumination wavelength, NA is the lens numerical aperture, and k1 and k2 are process constants.
In general, a shorter wavelength light source and/or a higher numerical aperture lens afford a higher-resolution system. State-of-the-art light sources provide a beam having a wavelength of approximately 193 nanometers. As stated above, the semiconductor industry has been driving the need for critical feature sizes to decrease exponentially over time, while exposure light source wavelengths have only been decreasing linearly with time.
Carrying this scenario forward, current and future optical lithography will be required to image feature sizes of sub-wavelength dimensions. Sub-wavelength optical lithography has been introduced with the 180-nm Node device generation, fabricated using 248-nm optical lithography.
As noted above, the numerical aperture of the lens also drives resolution. In this field, the cost of lenses having very high numerical apertures (“NA”) approaching 0.9 to 1.0 is very high. Moreover, linear NA increases are not sufficient to maintain pace with the need for exponentially decreasing feature sizes.
To meet this demand, Resolution-Enhanced optical lithography Technologies (“RET”) have become popular as techniques for providing patterns with sub-wavelength resolution. These methods include off-axis illumination (“OAI”), optical proximity correction (“OPC”), and phase-shift masks (“PSMs”). Such resolution-enhanced optical lithography methods are especially useful for generating physical devices on a wafer that require small size and tight design tolerance. Examples of such physical devices are the gate length of a transistor or the dimensions of contact cuts formed in inter-layer dielectrics. However, the conventional RET methods face problems of layout complexity and data size, mask fabrication complexity and resulting cost, and optical proximity and spatial frequency effects which are discussed below.
In many circuit applications, it is an important design constraint that the respective sizes of the narrow lines are consistent throughout the circuit. For example, in a semiconductor device, the narrow lines may form transistor gates, and it is important that the transistor gates are similar in size so that the circuit has consistent and predictable gate delay values.
In general, in any optical lithography technique, the resulting optical image intensity is a function of the proximity of features. Contrast is lost as feature pitch values decrease. As a result, the resulting size of features located in densely populated regions can be different than the size for those features that are isolated from the densely populated features. This is known as the “optical proximity” effect.
With respect to optical proximity effect, the critical dimension of features depends on feature density. Moreover, optical proximity effects can become more severe in sub-wavelength lithography. The optical proximity effects can result in dense lines 261 and an isolated line 262 on wafer 26 being printed with different sizes, even if the same size on the mask, as illustrated in FIG. 4, or dense contacts 263 and an isolated contact 264 on wafer 26 being printed with different sizes, even if the same size on the mask, as illustrated in FIG. 5. Since the performance of the circuit depends on the size and size tolerance of the gates, this is an undesirable result.
Spatial frequency effects are caused by the “low-pass filter” behavior of a projection lithography lens wherein high spatial frequencies do not pass through the lens. This results in corner rounding and line end shortening. An example of this effect is illustrated in FIG. 6. As illustrated in FIG. 6, a desired image is represented by mask 2200, but the actual image pattern 265 on the wafer is shortened and rounded.
To compensate for optical proximity and spatial frequency effects, additional features have been conventionally introduced on the mask that can involve both printable as well as sub-resolution elements. In these methods, extra features such as serifs, mousebites, hammerheads, and scattering bars are added to the mask features in order to correct for optical proximity effects and other spatial frequency effects. These conventional methods involve sophisticated algorithms with very large data size, as different corrections are required for each separation distance between the features. For this reason, conventional feature size correction (“OPC” or optical proximity correction) is a costly and time-consuming process.
Conventional OPC generally involves the processing of an enormous data volume. The hierarchical data processing algorithms used for conventional circuit design are of limited utility because optical proximity effects are based on the nature of geometries surrounding a particular circuit element. For example, a 1× AND gate surrounded by registers on all sides will perform differently than a 1× AND gate surrounded by other 1× AND gates. Other examples of conventional lithography methods addressing the need for finer features or higher-resolution features will be discussed below.
U.S. Pat. No. 5,415,835-B1 (“Brueck et al.”) discusses a method of fine-line imaging based on laser interferometry. In Brueck et al., dense gratings formed by laser interferometry are customized by additional exposures using both interferometric and conventional lithography. Brueck et al. does not address optical proximity and spatial frequency effect problems thus limiting the ultimate density and flexibility of the patterns produced. In addition, the multiple exposures are not substantially independent in the optical sense due to the resist's “memory” of previous exposure patterns. It is also difficult to make an arbitrary two-dimensional pattern in this way.
EP-0915384-A2 (“Suzuki et al.”) expands upon interferometric lithography. Suzuki et al. discloses using interferometric one-dimensional gratings to realize fine-line lithography together with subsequent customization exposures using multiplex (sub-threshold) exposure doses. Suzuki et al. does not address optical proximity and spatial frequency effect problems thus limiting the ultimate density and flexibility of the patterns produced. The multiple exposures are not substantially optically independent due to the resist's “memory” of the previous exposures. It is also difficult to realize an arbitrary 2D pattern with this method. Since the fine features are only realized in one orientation, it is difficult to form patterns with fine features in both the x & y directions.
WO-1/06320-A1 (“Levenson”) discloses re-usable “master” fine feature phase-shift masks that can be customized by multiple exposure methods using conventional masks. Levenson discloses a “trade-off between a maximum density of features against the cost for low volume runs.” Thus, the target application is primarily ASIC and thin-film head patterns where the pattern density is not too great. Just as in the previous patents discussed above, this method does not mitigate optical proximity and spatial frequency effects. It does not include substantially independent multiple exposures.
Finally, U.S. Pat. No. 6,184,151-B1 (“Adair et al.”) discloses a method for forming square shape images wherein a first plurality of lines running in a first direction is defined in a first layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating sharp corners wherever the first and second layers intersect and in open areas between the lines. This process addresses the spatial frequency effect problems of corner rounding and line-end shortening, but does not resolve the optical proximity effect problem. The control of fine features through pitch is important in order to realize the maximum pattern density and flexibility for applications.
One of the most common commercial implementations of phase shift mask technology is the double exposure method. In this method, the critical features are imaged using a phase shift mask and the non-critical and trim features are imaged in a second exposure using a conventional chrome-on-glass mask.
An example of a double exposure phase shift method is illustrated in FIG. 7. Double exposure imaging has become an accepted method in the field of resolution enhancement lithography.
In this method, fine features 42 are typically imaged on the substrate 26 in the first exposure, using a phase shift mask 31, and definition of other features 204 and trimming of undesired phase edges are performed in a second exposure using a trim mask 38. The phase shift mask may contain additional opaque features 203.
A typical double exposure phase shift method uses a conventional chrome-on-glass binary photomask for the trim mask 38. In this case, chrome regions 40 on the trim mask 38 prevent desired features produced by the phase shift mask 31 from being exposed in the trim exposure.
Multiple critical dimensions are typically formed by varying the width of a chrome regulator structure 201 placed at each phase edge 36, as is illustrated in the mask of FIGS. 8 and 9.
More specifically, an alternating aperture phase shift mask, which has chrome regulators at each phase edge, is illustrated in FIGS. 8 and 9. FIG. 8 is a top view and FIG. 9 is a cross sectional view. Unlike the chromeless phase shift mask, the alternating aperture phase shift mask 122 has chrome regulators 201 placed at each phase edge 36.
Phase shift masks work by employing the principle of destructive interference of light to generate fine dark lines in photoresist. A phase shift photomask is typically made of quartz (SiO2) in which features are etched to a depth corresponding to a 180-degree phase difference for the illumination light wavelength used. The equation for determining etch depth for optimum destructive interference is:d=λ/2(n−1)  1)where d is the etch depth, λ is the exposure wavelength and n is the index of refraction of the glass mask at the exposure wavelength.
Upon illumination by the lithography apparatus as shown in FIG. 1, each feature edge 36 forms a fine dark line in the photoresist 28. Note that since these dark line features correspond to phase boundaries 36, these dark line features are topologically closed which has lead to the development of double exposure phase shift methods in order to trim away the undesired fine lines in a second exposure.
In this process, the critical features are imaged using a phase shift mask and non-critical and trim features are imaged in a second exposure using a conventional chrome-on-glass mask. One of the challenges of this approach is the imaging of a variety of near minimum width feature sizes, by varying widths of chrome regulator features at each phase transition.
As feature sizes continue to scale into the deep sub-wavelength regime, it becomes more difficult to fabricate multiple sizes of critical dimension features by varying chrome regulator width. In addition, state of the art chromeless phase shift lithography methods, which are capable of the largest resolution enhancement, cannot be used to image multiple fine feature critical dimensions in a single die.
Another example of a double exposure method is disclosed in U.S. Pat. No. 5,858,580 (Wang et al.). Wang et al. discloses creating a phase shifting mask and a structure mask for shrinking integrated circuit designs. One disclosed embodiment includes using a two-mask process. The first mask is a phase shift mask and the second mask is a single-phase structure mask. The phase shift mask primarily defines regions requiring phase shifting. The single-phase structure mask primarily defines regions not requiring phase shifting. The single-phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
As feature sizes continue to move ever deeper into the sub-wavelength regime, it becomes increasingly difficult to image a variety of critical dimensions using this method. In addition, chromeless phase shift masks, which have great resolution enhancement potential, cannot be used to image multiple critical dimensions
The methods discussed above are also applicable to the case where fine features are defined using interferometric processes or using nanoimprint processes. In interferometric technology, a substrate is exposed interferometrically, using two or more coherent illumination sources to generate an interference pattern on the substrate. In nanoimprint technology, a topographic pattern on a master template is transferred to a substrate by direct mechanical contact.
It is therefore desirable to develop a method that mitigates optical proximity and spatial frequency effects without adding complex optical proximity correction features to the mask, while preserving the resolution enhancement aspects required by sub-wavelength lithography. This is especially desirable since conventional optical proximity correction approaches are becoming quite difficult to implement as imaging requirements continue to move deeper into the sub-wavelength regime.
It is also desirable to eliminate basic optical proximity effects, involving the defining or forming of fine lines in the x and y directions through a variety of pitch values and to minimize spatial frequency effects such as corner rounding and line-end shortening.
It is further desirable to simplify circuit layout and mask fabrication, resulting in lower cost and substantially decreased data volume required for a typical design, thereby allowing for design of standard cells that can be accurately characterized independently of their eventual placement in a larger circuit.
Moreover, it is desirable to develop a method that incorporates sub-resolution features to allow for lithographic definition of features with locally variable critical dimension, which can be used in a variety of lithographic processes, such as phase shift lithography, interferometric lithography, or nanoimprint technology.
It is also desirable to provide local control of the effective exposure dose that defines the critical dimension of the feature so that a wide variety of small features can be imaged without the need for chrome regulators or additional exposures.
It is further desirable to develop a method that incorporates sub-resolution features to allow for lithographic definition of features with locally variable critical dimension, which can be used in customizing a master pattern on an individual substrate wherein the master pattern was formed using a master template and nanoimprint technology.
Lastly, it is desirable to develop a method that incorporates mask feature size bias to achieve tunable transmission in the range from 0 to 1.0 (normalized image intensity) when the feature size is near the resolution limit, which can be used in a variety of lithographic processes, such as phase shift lithography, interferometric lithography, or nanoimprint technology.